Method of reducing a critical dimension of a semiconductor device

ABSTRACT

The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate layer over a substrate, forming a hard mask layer over a gate layer, forming a first material layer over the hard mask layer, forming a patterned photoresist layer having an opening over the first material layer, etching the first material layer through a cycle including forming a second material layer over the semiconductor device and etching the first and second material layers, repeating the cycle until the hard mask layer is exposed by a reduced opening, the reduced opening formed in a last cycle, etching the hard mask layer beneath the second opening to expose the gate layer, and patterning the gate layer using the hard mask layer. An etching selectivity of the first and second material layers is smaller than an etching selectivity of the second material layer and the photoresist layer.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. Technological advances in IC materials and design have producedgenerations of ICs where each generation has smaller and more complexcircuits than the previous generation. However, these advances haveincreased the complexity of processing and manufacturing ICs and, forthese advances to be realized, similar developments in IC processing andmanufacturing are needed. In the course of IC evolution, functionaldensity (i.e., the number of interconnected devices per chip area) hasgenerally increased while geometry size (i.e., the smallest component(or line) that can be created using a fabrication process) hasdecreased. At the same time, spacing between devices on a chip also hasshrunk to accommodate a greater functional density. For example, in amemory chip such as an SRAM chip, a gate layer is processed to form aline that may be referred to as a gate line. The gate line is dividedinto multiple portions in a later processing step, each portion froms agate of a transistor device. The spacing between these divided gate lineportions may be referred to as a gate line-end spacing. The gateline-end spacing may be considered a critical dimension (CD) of a chip.To increase the transistor count on the SRAM chip, a smaller CD such asa smaller gate line-end spacing is desired. However, it may be difficultto reduce the critical dimension to a desired size by relying onlithography technologies alone. Other methods of reducing the CD mayinclude a tapered hard mask profile but this suffers drawbacks such as abridge defect or a mushroom defect, which could cause shorting betweentransistor devices or otherwise degrade the IC chip's performance.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isemphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIG. 1 is a flowchart illustrating a method for fabricating asemiconductor device to reduce a critical dimension according to variousaspects of the present disclosure;

FIGS. 2A to 15A illustrate top views of a semiconductor device atvarious stages of fabrication according to the method of FIG. 1; and

FIGS. 2B to 15B illustrate cross-sectional views of a semiconductordevice at various stages of fabrication according to the method of FIG.1.

SUMMARY

Provided is a method of fabricating a semiconductor device. A gate layeris formed over a semiconductor substrate. A patterned hard mask layer isformed over the gate layer. A first material layer is formed over thehard mask layer. A patterned photoresist layer having a first opening isformed over the first material layer. A portion of the first materiallayer beneath the first opening is removed through a cycle. The cycleincludes forming a second material layer over the photoresist layer andthe first material layer, and etching the second material layer and thefirst material layer. The cycle is repeated until the hard mask layer isexposed by a second opening in the first material layer, where thesecond opening is formed in a last cycle and is smaller than the firstopening. A portion of the hard mask layer beneath the second opening isetched to expose the gate layer. The gate layer is patterned using thehard mask layer. In this method, a first etching selectivity of thefirst and second material layers is smaller than a second etchingselectivity of the second material layer and the photoresist layer.

Also provided is another method of fabricating a semiconductor device.The method includes forming a first material layer over the asemiconductor substrate, forming a hard mask layer over the firstmaterial layer, forming a second material layer over the hard masklayer, patterning a photoresist layer to define a first opening over thesecond material layer, performing etching processes and coatingprocesses to form a second opening in the second material layer, thesecond opening being smaller than the first opening, removing a portionof the hard mask layer within the second opening to expose the firstmaterial layer, removing the various layers overlying a remainingportion of the hard mask layer, and pattering the first material layerwith the remaining portion of the hard mask layer. Each of the coatingprocesses includes partially filling the first opening with a thirdmaterial layer thereby reducing the first opening and each of theetching processes includes an anisotropic etching process thatsubstantially leaves the third material layer disposed on sidewalls ofthe first opening and does not etch the patterned photoresist layer.

Further provided is yet another method of fabricating a semiconductordevice. A gate layer is formed over a semiconductor substrate. Apatterned hard mask layer is formed over the gate layer. A firstmaterial layer is formed over the patterned hard mask layer. A patternedphotoresist layer having an opening is formed over the first materiallayer. A plurality of cycles are performed until a portion of thepatterned hard mask layer is exposed, each cycle includes etching aportion of the first material layer within the opening and coating asecond material layer over the photoresist layer and the first materiallayer, partially filling the opening and reducing a dimension of theopening. The portion of the patterned hard mask layer is etched toexpose the gate layer. The gate layer is patterned with the etched hardmask layer. The method includes a first etching selectivity of the firstand second material layers that is smaller than a second etchingselectivity of the first material layer and the photoresist layer.

DETAILED DESCRIPTION

It is understood that the following disclosure provides many differentembodiments, or examples, for implementing different features of variousembodiments. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Forexample, the formation of a first feature over or on a second feature inthe description that follows may include embodiments in which the firstand second features are formed in direct contact, and may also includeembodiments in which additional features may be formed between the firstand second features, such that the first and second features may not bein direct contact. In addition, the present disclosure may repeatreference numerals and/or letters in the various examples. Thisrepetition is for the purpose of simplicity and clarity and does not initself dictate a relationship between the various embodiments and/orconfigurations discussed.

Illustrated in FIG. 1 is a flowchart of a method 100 for reducing acritical dimension (CD) of a semiconductor device. FIGS. 2A-15A andFIGS. 2B-15B are top views and cross-sectional views, respectively, thatillustrate one embodiment of a semiconductor device 200 during variousfabrication stages. The semiconductor device 200 may be an integratedcircuit (IC) chip, system on chip (SoC), or portion thereof, that mayinclude various passive and active microelectronic devices such asresistors, capacitors, inductors, diodes, metal-oxide semiconductorfield effect transistors (MOSFET), complementary metal-oxidesemiconductor (CMOS) transistors, bipolar junction transistors (BJT),laterally diffused MOS (LDMOS) transistors, high power MOS transistors,or other types of transistors. In one embodiment of the presentdisclosure, the semiconductor device 200 is an SRAM device. It isunderstood that FIGS. 2A to 15A and FIGS. 2B to 15B have been simplifiedfor a better understanding of the inventive concepts of the presentdisclosure. Accordingly, it should be noted that additional processesmay be provided before, during, and after the method 100 of FIG. 1, andthat some other processes may only be briefly described herein.

Referring to FIG. 1, the method 100 begins with block 110 in which agate layer is formed over a semiconductor substrate. The method 100continues with block 120 in which a patterned hard mask layer is formedover the gate layer. The method 100 continues with block 130 in which afirst material layer is formed over the hard mask layer. The method 100continues with block 140 in which a patterned photoresist layer havingan opening is formed over the first material layer. The method 100continues with block 150 in which a plurality of cycles are performed tothe semiconductor device. Each cycle includes an etching process to etchaway a portion of the first material layer within the opening. Eachcycle also includes a coating process to coat a second material layerover the photoresist layer and the first material layer. The coatingprocess partially fills the opening and reduces a dimension of theopening. The last cycle exposes the hard mask layer by a reducedopening. The method 100 continues with block 160 in which a portion ofthe hard mask layer within the reduced opening is etched to expose thegate layer. The method 100 continues with block 170 in which the gatelayer is patterned with the etched hard mask layer.

Referring to FIGS. 2A and 2B, illustrated are a top view and across-sectional view, respectively, of the semiconductor device 200being fabricated according to the method 100. The dashed lines and thearrows shown in the top view illustrate the direction at which thecross-sectional view is observed. The semiconductor device 200 includesa substrate 210. The substrate 210 may be a semiconductor wafer. Forexample, the substrate 210 may include silicon. The substrate 210 mayalternatively be made of some other suitable elementary semiconductor,such as diamond or germanium; a suitable compound semiconductor, such assilicon carbide, indium arsenide, or indium phosphide; or a suitablealloy semiconductor, such as silicon germanium carbide, gallium arsenicphosphide, or gallium indium phosphide. Alternatively, the substrate 210may include a non-semiconductor material such as a glass substrate forthin-film-transistor liquid crystal display (TFT-LCD) devices, or fusedquartz or calcium fluoride for a photomask (mask). The substrate 210 mayinclude various doped regions, dielectric features, and multilevelinterconnects. In one embodiment, the substrate 210 includes variousdoped features for various microelectronic components, such as acomplementary metal-oxide-semiconductor field-effect transistor(CMOSFET), imaging sensor, memory cell, and/or capacitive element. Inanother embodiment, the substrate 210 includes conductive materialfeatures and dielectric material features configured for coupling andisolating various microelectronic components, respectively.

A gate layer comprising a gate dielectric layer 212 and a gate electrodelayer 214 is formed on the substrate 210. The gate layer may bepatterned in a later processing step to form one or more gate lines. Forexample, the gate layer may be patterned to form gate lines for an SRAMdevice. In the present embodiment, the gate dielectric layer 212includes silicon oxide, and the gate electrode layer includespolysilicon. In an alternative embodiment, the gate dielectric layer 212includes a high-K material such as hafnium oxide (HfO₂), hafnium siliconoxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalumoxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide(HfZrO), or combinations thereof. The gate electrode layer 214 in thealternative embodiment includes a work function metal such as titaniumnitride (TiN) or tantalum nitride (TaN) and a conductive material suchas aluminum (Al), copper (Cu), tungsten (W), nickel (Ni), orcombinations thereof. The gate dielectric layer 212 and the gateelectrode layer 214 may be formed by various deposition techniques suchas physical vapor deposition (PVD), chemical vapor deposition (CVD),atomic layer deposition (ALD), plating, or other suitable techniques.

A hard mask layer 216 is then formed on the gate electrode layer 214.The hard mask layer 216 may be used to pattern the gate electrode layer214 and may include a dielectric material such as silicon oxide, siliconnitride, silicon oxynitride, or silicon carbide. In the presentembodiment, the hard mask layer 216 is formed with tetraethylorthosilicate (TEOS). The hard mask layer 216 may be formed by variousdeposition techniques such as PVD, CVD, ALD, or other suitabletechniques. The hard mask layer 216 is then patterned by aphotolithography process to form a protective hard mask that may be usedto pattern a gate line later. In the present embodiment, the patternedhard mask layer 216 has a rectangular shape, as shown by the top view inFIG. 2A. The photolithography process may include forming a photoresistlayer (not shown in FIG. 2A or 2B) on the hard mask layer 216 and thenperforming various etching and stripping processes to pattern the hardmask layer 216, the details of which are not discussed herein. It isunderstood that the hard mask layer 216 is elevated above the gateelectrode layer 214 at this stage of fabrication. Hence, the top view inFIG. 2A shows the gate electrode layer 214 on either side of thepatterned hard mask layer 216. It is also understood that the patternedhard mask layer 216 spans along an X direction, as is shown in FIG. 2A.The patterned hard mask layer will remain in the X direction insubsequent figures. Alternatively stated, the viewing angle of thesubsequent figures will not be rotated. Further, it is understood thatin an alternative embodiment, the gate electrode layer 214 is alsopatterned by the patterned hard mask layer 216 before additionalprocessing steps are performed. In the alternative embodiment, the gateelectrode layer would be patterned to take on the shape of the hard masklayer 216, which would resemble a rectangle spanning along the Xdirection.

Referring now to FIGS. 3A and 3B, a material layer 218 is formed overthe hard mask layer 216. In the present embodiment, the material layer218 is a bottom anti-reflective coating (BARC) layer. In one example,the BARC layer includes an organic material known in the art. Theorganic BARC material may be formed on the substrate by a spin-oncoating process, resulting in a substantially flat surface. In analternative embodiment, the material layer 218 is an anti-reflectivecoating (ARC) layer. The material layer 218 may function as ananti-reflection coating layer during later lithography exposureprocesses and additionally as a mask layer during later etchingprocesses to open the hard mask layer 216. The material layer 218 may beformed by spin-coating or other suitable processes. The process used toform the material layer 218 may be tuned to control a thickness 219 ofthe material layer 218. It is understood that although it cannot be seenfrom the top view of FIG. 3A, portions of the material layer 218 arealso formed on either side of the patterned hard mask layer 216, so thatportions of the material layer 218 are covering the gate electrode layer214.

A photoresist layer 220 is then formed on the material layer 218. Thephotoresist layer 220 may be formed by photolithography, immersionlithography, ion-beam writing, or other suitable processes. For example,the photolithography process may include spin-coating, soft-baking,exposure, post-baking, developing, rinsing, drying, and other suitableprocess.

Referring now to FIGS. 4A and 4B, a photolithography process 221 is usedto pattern the photoresist layer 220. The photolithography process 221includes exposing a portion of the photoresist layer 220 whileprotecting another portion of the photoresist layer 220 with aphotomask. After the photolithography process 221 is performed, anopening 222A is formed in the photoresist layer 220. The opening 222Amay be referred to as an initial opening 222A. The initial opening 222Ahas a dimension 224A. The dimension 224A may also be referred to as aninitial dimension 224A. In the present embodiment, the initial dimension224A may be greater than about 60 nanometers (nm). As is illustratedfrom the top view of FIG. 4A, the opening 222A is formed by essentiallycutting the photoresist layer 220 along a Y direction (shown in FIG. 4A)that is perpendicular to the X direction along which the patterned hardmask layer 216 spans.

Referring now to FIGS. 5A and 5B, an etching process 235 is performed tothe semiconductor device 200 to remove a portion of the material layer218. In the present embodiment, the etching process 235 includes a dryetching process implemented in an etching chamber using processparameters including a radio frequency (RF) source power ranging fromabout 400 W to about 1600 W, preferably about 800 W, and a bias powerranging from about 50 W to about 200 W, preferably about 100 W. Theetching chamber also operates with a pressure ranging from about 6 mTorrto about 24 mTorr, preferably about 12 mTorr. A plasma gas mixturehaving argon, CH_(x), (where x may be 1, 2, 3, 4 . . . ) and nitrogen isused as an etchant. In the present embodiment, the plasma gas mixtureincludes an NR gas that is formed by a mixture of argon and CH₄. The NRgas has a flow rate ranging from about 25 sccm to about 100 sccm,preferably about 50 sccm. The NR gas in the present embodiment alsoincludes a composition of about 96% argon and about 4% CH₄. The nitrogencomponent of the plasma gas mixture has a flow rate ranging from about50 sccm to about 200 sccm, preferably about 100 sccm in the presentembodiment. In alternative embodiments, other chemicals such as Cl₂,HBr, O₂, CH₄, CHF₃, CH₂F₂, or combinations thereof, may be used as anetchant. During the etching process 235, the substrate 210 is secured byan electronic chuck (E-chuck) for holding and moving the substrate 210during processing. The E-chuck in the present embodiment has differenttemperatures in different zones. Near a center zone of the E-chuck, thetemperature is about 38 degrees Celsius (° C.). Between the center zoneand an edge zone of the E-chuck (referred to as an intermediate zone),the temperature is about 32° C. Near the edge zone of the E-chuck, thetemperature is about 20° C. The etching process 235 has an etching timeof about 2.5 to about 10 seconds, preferably about 5 seconds. Note alsothat the etching process 235 may also be performed in a depositionchamber such as a CVD or PVD chamber.

Different materials may have different etching rates (or how fast thematerial is etched away) for a given etching process such as the etchingprocess 235. An etching selectivity may be defined as a ratio of etchingrates between two materials for the given etching process. Thus, a highetching selectivity indicates that the two materials are etched away atsubstantially different rates, whereas a low etching selectivityapproaching 1 indicates that the two materials are etched away almost atthe same rate. In the present embodiment, the photoresist layer 220 andthe material layer 218 are selected such that the etching process 235includes a high etching selectivity (for example, between 10-30) of thematerial layer to the photoresist layer. In other words, the etchingprocess 235 etches the photoresist layer 220 and the material layer 218at different rates. In the present embodiment, the etching process 235etches the material layer 218 at a faster rate than the photoresistlayer 220. Hence, a portion of the material layer 218 beneath theinitial opening 222A is removed while the photoresist layer 220 remainssubstantially unetched. Also, since the etching process 235 is a dryetching process having a bias power, the etching process 235 etches thematerial layer 218 in an anisotropic fashion, meaning that the etchingoccurs mostly in a vertical direction, and little lateral etchingoccurs. Consequently, the initial opening 222A is extended downwardlyinto the material layer 218 while maintaining a substantially verticalprofile. The etching process 235 may be fine tuned to control the amountof the material layer 218 to be removed. It has also been observed thatthe etching process 235 may remove some defects along the edges of theinitial opening 222A, such as photoresist scum.

Referring now to FIGS. 6A and 6B, a coating process 245 is used to coata material layer 240A over the patterned photoresist layer 220 and thematerial layer 218 exposed by the opening 222A. The coating process 245reduces the opening 222A to an opening 222B having a reduced dimension224B. The material layer 240A includes a polymer material in the presentembodiment. The coating process 245 also includes a CVD or PVD processand is implemented in a deposition chamber. In the present embodiment,the deposition chamber is the same chamber as the etching chamber usedin the etching process 235. In other words, the etching process 235 andthe coating process 245 are performed in-situ. Also in the presentembodiment, the coating process 245 uses a radio frequency (RF) sourcepower ranging from about 300 W to about 1200 W, preferably about 600 W,and a bias power of about 0 W. The deposition chamber also operates witha pressure ranging from about 0.75 mTorr to about 3 mTorr, preferablyabout 1.5 mTorr. A plasma gas mixture of argon, CH_(x), and CH_(x)F_(x)(where x may be 1, 2, 3, 4 . . . ) is used to form the material layer240A. In the present embodiment, the plasma gas mixture includes the NRgas described above in the etching process 235, which has a gas flowrate ranging from about 25 sccm to about 100 sccm, preferably about 50sccm. The CH_(x)F_(x) gas component in the present embodiment is CH₂F₂,which has a flow rate ranging from about 10 sccm to about 40 sccm,preferably about 20 sccm. In alternative embodiments, other chemicalssuch as a mixture of argon and CH₄, CH₃F, or combinations thereof, maybe used to form the material layer 240A. During the coating process 245,the substrate 210 is also secured by the E-chuck. The E-chuck in thepresent embodiment has different temperatures in different zones. Near acenter zone of the E-chuck, the temperature is about 38° C. Between thecenter zone and an edge zone of the E-chuck (referred to as anintermediate zone), the temperature is about 32° C. Near the edge zoneof the E-chuck, the temperature is about 20° C. The coating process 245has a coating time of about 8 to about 32 seconds, preferably about 16seconds. The coating process 245 is operable to control a thickness 247of the material layer 240A, so that the dimension 224B of the opening222B may be tuned based on the thickness 247. In the present embodiment,the dimension 224B is approximately equal to (the initial dimension224A)−2×(thickness 247 of the material layer 240A).

The etching process 235 and the coating process 245 together may bereferred to as an etching-coating cycle. The etching-coating cycle maybe performed several times to further reduce the initial dimension 224Aof the initial opening 222A and to etch away enough of the materiallayer 218 to expose the hard mask layer 216. The exact number of theetching-coating cycles may vary depending on design and processingrequirements. For instance, if a small critical dimension is desired bydesign requirements, the etching-coating cycle may be repeated moretimes to reduce the initial opening 224A down to the desired criticaldimension. The reduced opening has a dimension approximately equal to (adimension of the initial opening)−2×[a sum of (a thickness of a materiallayer coated during each coating process)]. For the sake of example, afew more iterations of the etching-coating cycle is discussed below andillustrated by FIGS. 7A-11A and 7B-11B.

Referring now to FIGS. 7A to 7B, an etching process 255 is performed tothe semiconductor device 200 to remove portions of the material layer240A over the photoresist layer 220 and the material layer 218. Theetching process 255 is similar to the etching process 235 describedabove and uses similar process parameters, with the exception that theetching time ranges from about 8 seconds to about 32 seconds, preferablyabout 16 seconds. The material layers 218 and 240A are selected suchthat the etching process includes a low etching selectivity of thematerial layer 218 to the material layer 240A. For example, the etchingselectivity between the material layers 218 and 240A may be close to 1(i.e., substantially the same etching rates). Meanwhile, the materiallayers 218 and 240A are selected such that the etching process 255 has ahigh etching selectivity with respect to the photoresist layer 220. Forexample, the etching selectivity of the material layer 218 (or thematerial layer 240A) to the photoresist layer 220 may be substantiallygreater than 1 (for example, between 10-30). Hence, the etching process255 is operable to remove a portion of the material layer 218 within theopening 222B once the portion of the material layer 240A covering thematerial layer 218 has been etched away. At the same time, thephotoresist layer 220 remains substantially unetched. The extent thatthe material layer 218 is etched (or the amount of the material layer218 that is removed) may be controlled by process parameters such as anetching time of the etching process 255. Also note that the etchingprocess 255 is a directional dry etching process, hence the etchingdirection is mostly vertical in an anisotropic fashion, where littlelateral etching occurs. As such, portions of the material layer 240A onthe sidewalls of the opening 222B remain mostly unetched by the etchingprocess 255, and the opening 222B maintains a substantially verticalprofile.

Referring now to FIGS. 8A to 8B, a coating process 265 is used to coat amaterial layer 240B over the patterned photoresist layer 220 and thematerial layer 218 exposed by the opening 222B. The coating process 265reduces the opening 222B to an opening 222C having a reduced dimension224C. The material layer 240B includes substantially the same materialas the material layer 240A described above. The coating process 265 isalso similar to the coating process 245 described above and uses similarprocess parameters. Process parameters such as coating time of thecoating process 265 may be tuned to control a thickness 267 of thematerial layer 240B. After the coating process 265 is performed, thedimension 224C is further reduced to be approximately equal to (theprevious dimension 224B)−2×(thickness 267 of the material layer 240B).Alternatively, the reduced dimension 224C may be expressed as beingapproximately equal to (the original dimension 224A)−2×[(thickness 247of the material layer 240A)+(thickness 267 of the material layer 240B)].

Referring now to FIGS. 9A to 9B, an etching process 275 is performed onthe semiconductor device 200 to remove portions of the material layer240B over the photoresist layer 220 and the material layer 218. Theetching process 275 is similar to the etching process 255 describedabove and uses similar process parameters. The extent that the materiallayer 218 is etched (or the amount of the material layer 218 that isremoved) may be controlled by process parameters such as etching time ofthe etching process 275. Also note that the etching process 275 is adirectional dry etching process, hence the etching direction is mostlyvertical, and little lateral etching occurs, and the opening 222Cmaintains a substantially vertical profile. As such, portions of thematerial layers 240B on the sidewalls of the opening 222C remain mostlyunetched by the etching process 275.

Referring now to FIGS. 10A to 10B, a coating process 285 is used to coata material layer 240C over the patterned photoresist layer 220 and thematerial layer 218 exposed by the opening 222C. The coating process 265reduces the opening 222C to an opening 222D having a reduced dimension224D. The material layer 240C includes substantially the same materialas the material layers 240A and 240B described above. The coatingprocess 285 is also similar to the coating processes 245 and 265described above and uses similar process parameters. Process parameterssuch as coating time of the coating process 285 may also be tuned tocontrol a thickness 287 of the material layer 240C. After the coatingprocess 285 is performed, the dimension 224D is further reduced to beapproximately equal to (the previous dimension 224C)−2×(thickness 287 ofthe material layer 240C). Alternatively, the reduced dimension 224D ofthe opening 222D may be expressed as being approximately equal to (theoriginal dimension 224A)−2×[(thickness 247 of the material layer240A)+(thickness 267 of the material layer 240B)+(thickness 287 of thematerial layer 240C)]. In the present embodiment, the dimension 224Ddoes not exceed 40 nm, preferably about 35 nm. It is understood that thespecified dimension of the opening 222D is a mere example and smallerdimensions may be achieved by the methods disclosed herein.

Referring now to FIGS. 11A to 11B, an etching process 295 is performedon the semiconductor device 200 to remove portions of the material layer240C over the photoresist layer 220 and the material layer 218. Theetching process 295 is similar to the etching processes 255 and 275described above and uses similar process parameters. The extent that thematerial layer 218 is etched (or the amount of the material layer 218that is removed) may be controlled by process parameters such as etchingtime of the etching process 295. Also note that the etching process 295is a directional dry etching process, hence the etching direction ismostly vertical, and little lateral etching occurs, and the opening 222Dmaintains a substantially vertical profile. As such, portions of thematerial layer 240C on the sidewalls of the opening 222D remain mostlyunetched by the etching process 295. In the present embodiment, theetching process 295 substantially etches through a portion of thematerial layer 218 such that a portion of the hard mask layer 216 isexposed by the opening 222D. This can also be seen in the top view ofFIG. 11A, where the rectangular shaped portion in the middle representsan area of the hard mask layer 216 exposed by the opening 222D. Thedashed lines extending laterally from the rectangular shaped portionrepresent portions of the hard mask layer 216 not observable from thetop view yet, since they are covered by portions of the material layer218 as well as portions of the photoresist layer 220 at this stage ofprocessing. A profile of the hard mask layer 216 outlined by the dashedlines in the top view in FIG. 11A is displayed for the sake of clarityand ease of understanding. From FIG. 11A, it can be seen that the hardmask layer 216 is essentially perpendicular to a “trench” formed by theopening 222D, where the hard mask layer 216 spans along the X direction,and the “trench” formed by the opening 222D spans along the Y direction.

It is also understood that in addition to removing the material layer218 over the hard mask layer 216 to expose the hard mask layer 216, theetching process 295 may also remove portions of the material layer 218on either side of the hard mask layer 216 within the opening 222D, suchthat portions of the electrode layer 214 on either side of the hard masklayer 216 are exposed by the opening 222D. This is what is shown by thetop view of FIG. 11A. In an alternative embodiment, the portions of thematerial layer 218 on either side of the hard mask layer 216 within theopening 222D are not removed until later processes. In this alternativeembodiment, portions of the electrode layer 214 are not yet exposed bythe opening 222D at the end of the etching process 295.

As mentioned above, the opening 222D now has a reduced dimension 224Dthat is smaller than the initial dimension 224A of the initial opening222A. The opening 222D may be used to define a critical dimension suchas a gate line-end spacing in later processing steps. In semiconductorfabrication, it is desired to have a small critical dimension so that achip may have a higher transistor density. However, the criticaldimension (which is correlated to the spacing 222A-222D) has beenlimited by lithography technologies. For example, it is difficult toachieve a small critical dimension such as a gate line-end spacingaround 35 nm, by using lithography alone.

Referring now to FIGS. 12A to 12B, an etching process 305 is performedto the semiconductor device 200 to etch away a portion of the hard masklayer 216 beneath the opening 222D. In the present embodiment, theetching process 305 is a dry etching process using a fluorine-containingplasma as an etchant. The etching process 305 is operable to etch awaythe portion of the hard mask layer 216 in a substantially anisotropicfashion, so that the opening 222D is extended downward while maintainingits substantially vertical profile. In the present embodiment, the gateelectrode layer 214 is exposed by the opening 222D after the etchingprocess 305 is performed. The hard mask layer 216 is “severed” or“divided,” and the remaining portions of the hard mask layer 216 areillustrated by the dashed lines in the top view of FIG. 12A.

Referring now to FIGS. 13A to 13B, the remaining portions of thematerial layers 218 and 240A-C as well as the photoresist layer 220 areremoved by various stripping, ashing, and etching processes known in theart.

Referring now to FIGS. 14A to 14B, the hard mask layer 216 is used as amask to pattern the gate electrode layer 214 and the gate dielectriclayer 212 below. An etching process known in the art is used to etchaway a portion of the gate electrode layer 214 “not protected” (orexposed) by the hard mask layer 216 as well as a portion of the gatedielectric layer 212 below the gate electrode layer 214. The substrate210 is now covered by the remaining portions of the hard mask layer 216and portions of the gate electrode layer 214 “protected” (or covered) bythe hard mask layer 216 and portions of the gate dielectric layer 212below the gate electrode layer 214.

Referring now to FIGS. 15A to 15B, the hard mask layer 216 is removed byan etching process known in the art. The remaining portions of the gateelectrode layer 214 form two rectangular portions separated by theopening 222D having the dimension 224D. In the present embodiment, theremaining portions of the gate electrode layer 214 may form gates oftransistors and may be referred to gates 214. The dimension 224Dseparating the gates 214 may also be referred to as a gate line-endspacing, which is about 35 nm in the present embodiment. As mentionedabove, it is desirable to have a small gate line-end spacing so thatmore transistors may be packed on a chip. It has been observed that thepresent embodiment is operable to reduce a gate line-end spacing fromgreater than about 60 nm to about 35 nm. Also, since the presentembodiment forms a substantially vertical profile instead of a taperedprofile for the first material layer as well as the patterned hard mask216, it has been observed that bridging or mushroom defects aresubstantially reduced using the methods in the present embodiment.

It is also understood that additional processing steps may be performedto complete the fabrication of the semiconductor device 200. Forexample, source and drain regions 310 may be formed in the substrate 210on either side of the gate 214, as is shown in the top view of FIG. 15A,where the source and drain regions 310 are represented by dashed lines.Isolation structures such as shallow trench isolation regions may beformed to isolate various transistor devices which may each include agate 214 and source and drain regions 310. In addition, contacts may beformed on gates 214. It is also understood that although the presentembodiment involves forming a patterned hard mask layer 216 beforesevering it to form the opening 222D as the critical dimension, the hardmask layer 216 may be patterned after severing the hard mask layer 216in another embodiment. Further, although the method disclosed by thepresent embodiment reduces a gate line-end spacing for a semiconductordevice 200, it is only an example, and it is also understood that themethod disclosed may be used to reduce critical dimensions of othersemiconductor features and structures such as via holes or contacts.

In summary, the methods disclosed herein provide an effective andefficient approach for reducing a critical dimension such as a gateline-end spacing of a semiconductor device. The methods disclosed hereintake advantage of one or more etching-coating cycles to reduce anopening in the semiconductor device. In doing so, the present embodimentoffers several advantages over prior art devices, it being understoodthat different embodiments disclosed herein may have differentadvantages. One advantage of the present embodiment is that a criticaldimension in the semiconductor device, such as a gate line-end spacing,may be reduced to a dimension not achievable by relying on currentphotolithography technologies alone. Another advantage is that flexibleadjustments may be made to the etching and coating processes describedin the present embodiment to define a profile of the opening and thedimension of the opening. For example, a substantially vertical hardmask profile may be achieved, while little lateral etching occurs. Yetanother advantage is that bridging or mushroom defects associated withprevious methods may be substantially reduced. Furthermore, theprocesses outlined are compatible with a CMOS processing flow.

The foregoing has outlined features of several embodiments so that thoseskilled in the art may better understand the detailed description thatfollows. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions andalterations herein without departing from the spirit and scope of thepresent disclosure.

1. A method of fabricating a semiconductor device comprising: forming agate layer over a semiconductor substrate; forming a hard mask layerover the gate layer; forming a first material layer over the hard masklayer; forming a patterned photoresist layer having a first opening overthe first material layer; removing a portion of the first material layerbeneath the first opening through a processing cycle including: forminga second material layer over the photoresist layer and the firstmaterial layer; and etching the second material layer and the firstmaterial layer; repeating the processing cycle until the hard mask layeris exposed by a second opening in the first material layer, the secondopening being formed in a last processing cycle and smaller than thefirst opening; etching a portion of the hard mask layer beneath thesecond opening to expose the gate layer; and patterning the gate layerusing the hard mask layer; wherein a first etching selectivity of thefirst and second material layers is smaller than a second etchingselectivity of the second material layer and the photoresist layer. 2.The method of claim 1, wherein the hard mask layer includes siliconoxide, and the gate layer includes polysilicon.
 3. The method of claim1, wherein the first material layer includes a BARC layer having anorganic material, and the second material layer includes a polymerformed by a mixture that includes argon, CH_(x), and CH_(x)F_(x).
 4. Themethod of claim 1, wherein the processing cycle is performed in-situ. 5.The method of claim 1, wherein the first opening is greater than about60 nm, and the second opening is less than about 40 nm, and wherein boththe first and second openings have a substantially vertical profile. 6.The method of claim 1, further including after the etching the portionof the hard mask layer, removing remaining portions of the secondmaterial layer.
 7. A method of fabricating a semiconductor devicecomprising: forming a gate layer over a semiconductor substrate; forminga patterned hard mask layer over the gate layer; forming a firstmaterial layer over the patterned hard mask layer; forming a patternedphotoresist layer having an opening over the first material layer;performing a plurality of cycles until a portion of the patterned hardmask layer is exposed, each cycle including: etching a portion of thefirst material layer within the opening; and coating a second materiallayer over the photoresist layer and the first material layer, partiallyfilling the opening and reducing a dimension of the opening; etching theportion of the patterned hard mask layer to expose the gate layer; andpatterning the gate layer with the etched hard mask layer; wherein afirst etching selectivity of the first and second material layers issmaller than a second etching selectivity of the first material layerand the photoresist layer.
 8. The method of claim 7, wherein etching theportion of the first material layer and coating the second materiallayer are performed in-situ.
 9. The method of claim 7, wherein etchingthe portion of the first material layer includes a dry etching processusing a mixture that includes argon, CH_(x), and nitrogen.
 10. Themethod of claim 9, wherein the argon and CH_(x) each has a flow rate ofabout 50 sccm, and the nitrogen has a flow rate of about 100 sccm, andwherein the dry etching process includes a pressure of about 12 mTorr, asource power of about 800 W, and a bias power of about 100 W.
 11. Themethod of claim 10, wherein the dry etching process further includes anetching time of about 16 seconds and an E-chuck having temperatures ofabout 38° C. near a center zone, about 32° C. near an intermediate zone,and about 20° C. near an edge zone.
 12. The method of claim 7, whereinthe second material layer is formed by a coating process using argon,CH_(x), and CH_(x)F_(x), and wherein the argon and CH_(x) each has aflow rate of about 50 sccm, and the CH_(x)F_(x) has a flow rate of about100 seem, and wherein the coating process includes a pressure of about1.5 mTorr, a source power of about 600 W, and a bias power of about 0 W.13. The method of claim 12, wherein the coating process further includesa coating time of about 16 seconds and an E-chuck having temperatures ofabout 38° C. near a center zone, about 32° C. near an intermediate zone,and about 20° C. near an edge zone.
 14. The method of claim 7, whereinthe openings maintain a substantially vertical profile through theplurality of cycles.
 15. The method of claim 7, further including afterthe etching the portion of the hard mask layer, removing remainingportions of the first material layer, the second material layer, and thepatterned photoresist layer.
 16. A method of fabricating a semiconductordevice comprising: forming a first material layer over a semiconductorsubstrate; forming a hard mask layer over the first material layer;forming a second material layer over the hard mask layer; patterning aphotoresist layer to define a first opening over the second materiallayer; performing a plurality of etching processes and coating processesto form a second opening in the second material layer, the secondopening having a substantially vertical profile and being smaller thanthe first opening; removing a portion of the hard mask layer within thesecond opening to expose the first material layer; removing the variouslayers overlying a remaining portion of the hard mask layer; andpatterning the first material layer with the remaining portion of thehard mask layer; wherein each of the plurality of coating processesincludes partially filling the first opening with a third material layerthereby reducing the first opening; wherein each of the plurality ofetching processes includes an anisotropic etching process that does notremove a portion of the third material layer disposed on sidewalls ofthe first opening.
 17. The method of claim 16, wherein the secondmaterial layer includes a BARC layer, and wherein the third materiallayer includes a polymer.
 18. The method of claim 16, wherein theplurality of etching processes and coating processes are performedin-situ.
 19. The method of claim 18, wherein each of the plurality ofetching processes utilizes argon, CH_(x), and nitrogen, and wherein eachcoating process utilizes argon, CH_(x), and CH_(x)F_(x).
 20. The methodof claim 16, wherein the first material layer includes polysilicon, andwherein patterning the first material layer includes forming first andsecond gate structures, the first and second gate structures beingseparated in a first direction by a dimension substantially equal to adimension of the second opening; and further including: forming first,second, third, and fourth active regions, the first and second activeregions being disposed on either side of the first gate structure in asecond direction that is approximately perpendicular to the firstdirection, and the third and fourth active regions being disposed oneither side of the second gate structure in the second direction.